1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of accurately measuring a time parameter, such as the setup/hold time and the access time, of a synchronous memory device mounted on an LSI (large-scale integration) device together with synchronous logics integrated thereon.
2. Description of the Background Art
In general, a memory-logics LSI device, integrated on a semiconductor substrate, includes a memory or storage device, logics, an external signal switching circuit and a memory-logics interface (IF) signal switching circuit. Briefly describing the interconnection of these components, the memory-logics interface signal switching circuit is arranged between the memory device and the logics. The memory-logics interface signal switching circuit is supplied with an input signal from the logics on its input path to output the signal to the memory device from its output path. The memory-logics interface signal switching circuit is also supplied with a signal from the memory device on its other input path to deliver the signal to the logics from its other output path.
Between the external input/output pins of the integrated circuit and the logics, an external signal switching circuit is provided. The external signal switching circuit is supplied with a signal supplied from outside on its input path, to output the supplied signal from its output path to the external input/output pins. By the interconnection stated above, the memory-logics LSI device is thus adapted to transmit and receive the signals.
The memory-logics LSI device has a memory test mode evaluating the characteristics of the memory device. In the memory test mode, the external signal switching circuit and the memory-logics interface signal switching circuit of the memory-logics LSI device are made operative as a test interface circuit, and a test input path and a test output path are arranged to be directly used as an internal data transfer path without the intermediary of the logics disposed between the external signal switching circuit and the memory-logics interface signal switching circuit.
The memory configuration will now be described. The memory device includes a memory input/output unit and a memory controller, through which data are transferred to and from the synchronous memory. In particular, the memory input/output unit uses, for each input, an input buffer, a delay for timing adjustment and a flip-flop circuit, while using, for each output, an output buffer. In respect of clocks, an input buffer and a clock driver are provided. The flip-flop circuit used on the input side and the output buffer used on the output side are supplied with input clocks and output clocks, respectively.
The memory-logics LSI device structured as stated above makes the internal data transfer path operative to measure the setup/hold time and the access time of the memory device. The setup/hold time and the access time in the memory-logics LSI device are measured with the delay involved which is encountered on the internal signal paths such as the external signal switching circuit from the input/output pins to the memory device and the direct input/output path.
Several other examples of memory operational test have been proposed. The semiconductor integrated circuit device disclosed in Japanese patent laid-open publication No. 264675/1993 aims at improving the accuracy of the operational test of a memory device mounted on the integrated circuit device. In the circuit device, a memory device and a logic circuit are formed on the same semiconductor chip and an operational test of the memory device is carried out in response to an address signal entered from a terminal dedicated to testing on the chip. In response to this multi-bit address signal, entered from the terminal, the memory test circuit provides the input port of the memory device with the multi-bit address signal, and thereafter outputs a write control signal of a predetermined pulse duration to the memory device in response to the multi-bit address signal. That causes the operational test to be conducted without being affected by variations in the signal transfer time, thus improving accuracy in operational test.
The memory device integrated together with logics and the testing method therefor, disclosed in Japanese patent laid-open publication No. 174121/1999, intend to reduce the number of the transitions at the time of switching test modes to thereby improving the test efficiency and reducing the noise. The memory device is provided with an ordinary operational test mode for testing a memory core via a logic circuit, and a bypass test mode for entering information from an external pad without the intermediary of the logic circuit to directly test the memory core. The test circuit is thus used in common to the logic circuit and the memory core. The test selection information from a mode register or the test selection information from multiplexers is selected by another multiplexer, so that the selected information is supplied to the test circuit to enable the setting and the execution of the test mode.
The apparatus and method for testing a semiconductor integrated circuit, disclosed in Japanese patent laid-open publication No. 2002-162444, improve the situation in which the LSI device is not actually operative when the memory is tested to cause unforeseen operational troubles during actual use, or in which the memory and the random logics are tested independently of each other to thereby increase the cost for testing. For that aim, the memory device is supplied with a test signal separately from the logics, and the logics are supplied with an operating signal for intentionally being rendered operative. Hence, the operating state may be established closely to the actual operating state. In addition, the memory test and the scanning test may be conducted simultaneously, and therefore the test time may be shorter, whilst the cost for testing may also be reduced.
The case of evaluating memory characteristics in the memory-logics LSI device, indicated above, will now briefly be described. In measuring the access time by the above-indicated configuration, a clock signal is supplied over connections of the external input pins, external signal switching circuit, memory-logics interface signal switching circuit and memory input buffer. On the other hand, the output data from the memory device are supplied over connections of the memory-logics interface signal switching circuit, external signal switching circuit and external connection pins. Those connections cause the actual access time to be measured including the time required from inputting an external clock to outputting external data, that is, the delay time caused by the above-described circuits and the load on the connections.
Turning now to the setup/hold time, the input signal is supplied over the connections of the external input pins, external signal switching circuits, memory-logics interface signal switching circuit and memory input buffer to the flip-flop circuit of the memory device. In this case, the setup/hold time is actually measured including the difference in input timing between the external input pins for clock and input signals, that is, the skew ascribable to the physical difference between the transfer routes of the clock and the input signals. This time measurement did not correctly reflect the memory characteristics.
Japanese patent laid-open publication Nos. 264675/1993 and 2002-162444 deal with, as described above, measuring the time free from delay but the problem totally different from measuring the time free from. Japanese patent laid-open publication No. 174121/1999 discloses the bypass test mode indeed, and is silent about measurement of time free from delay described above.